High-speed SERDES (Serial/Deserial) technology has been under active development over the last 20 years. SERDES technology has been widely used in data storage systems, telecommunications, computer technologies and many other fields. A desire for higher transmission bandwidths and speeds through SERDES devices never stops. Ten years ago, designers struggled with designs reaching single lane transmission of 2 Gbps (gigabits per second) in CMOS technology. Presently, specifications for SERDES devices have passed 10 Gbps.
In a high-speed transceiver design, AC coupling in a channel between a transmitter connection and a receiver connection is preferred, and is often specified for proper functioning of the link. In DC coupled links, the signal is sensitive to duty cycle distortion due to the common-mode voltage mismatch between the transmitter and the receiver. At high transmission frequencies of 6 Gbps and beyond, where the signal loss is significant through the backplane, the signal damage resulting from the duty cycle distortion is permanent and is problematic for the receiver to recover.
Referring to FIG. 1, a perspective diagram of a conventional on-chip AC-coupled high speed circuit 80 is shown. The circuit 80 has a bump 82 connected to an AC capacitor 84 through a metal routing line 86, that presents a parasitic resistance (i.e., R_RTG) and a parasitic capacitance (i.e., C_RTG), all fabricated on a substrate 88. Additional circuitry 87 is commonly fabricated below the bump 82. A power/ground plane 90 commonly exists above the capacitor 84. The structure of the circuit 80 results in parasitic capacitances to the power/ground planes 88 and 90 as represented by (i) CP_BUMP (ii) C_RTG, (iii) CP1_P1, (iv) CP2_P1, (v) CP1_P2 and (vi) CP2_P2, as shown.
The capacitor 84 occupies a large silicon footprint. In many cases, the capacitor 84 dominates the total silicon budget. Furthermore, the bump 82 and the capacitor 84 contribute significant individual parasitic capacitances (often the top two dominating parasitic capacitances), weakening the overall high-speed performance of the circuit 80. Commonly, the line 86 may route hundreds of microns from the bump 82 to the capacitor 84 due to priority placement of various blocks relative to the bump 82. The long line 86 contributes to signal degradation that also limit the performance the circuit 80. Still further, the capacitor 84 is usually fabricated in the lower metal and polysilicon layers thereby creating routing channel congestion.